Through an official blog post, IBM Research today announced that it has developed industry-first silicon nanosheet transistors for the development of 5-nanometer chips. It has been developed in collaboration with Research Alliance partners, GlobalFoundaries and Samsung.
This development comes more than two years after IBM first showed off its 7-nanometer test node silicon chip, which included 20 billion transistors. The company plans to detail the process of developing these 5-nanometer chips at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan. This process and chips is still a prototype and is not being mass-produced for consumer systems as of yet — will not happen for another couple years.
Talking about this achievement, Arvind Krishna, senior VP, Hybrid Cloud and director, IBM Research said:
For business and society to meet the demands of cognitive and cloud computing in the coming years, advancement in semiconductor technology is essential. That’s why IBM aggressively pursues new and different architectures and materials that push the limits of this industry and brings them to market in technologies like mainframes and our cognitive systems.
Talking about this achievement, researchers mention that it will enable the humongous $330 billion chip industry to still continue following Moore’s Law — a prediction model presented by Intel co-founder and chairman emeritus Gordon Moore back in 1965. It mentions that the number of transistors per square inch of a chip would double within every couple years. And, IBM still seems to be fueling the concept with this innovation.
While even most of the advanced chips developed today employ the FinFET process, which includes a circuitry that’s 10-nanometer in width. This has steadily become the standard development architecture for chips in the current industry, which is led by Samsung and Qualcomm. They’ve already developed and deployed 10-nanometer chips that are powering most of the flagships that are being launched just recently.
Scientists working as part of the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture.
IBM has, however, ditched the standard design process in favor of a stacked nanosheet semiconductor architecture. It is using the same Extreme Ultraviolet (EUV) lithography approach, used to develop the previous-gen 7-nanometer chips, to include 30 billion transistors onto the chip. This technology makes it possible for IBM to continually adjust individual circuits to maximize all-round performance of the circuit.
The official blog post further states that the 5-nanometer chip technology can help deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. It is believed that the said architecture will introduce some huge improvements in future demands of artificial intelligence (AI) systems, virtual reality and mobile devices. It will also help accelerate the pace of development of cognitive computing, the Internet of Things (IoT), and other data-intensive applications as well.
